1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to techniques for manufacturing semiconductor devices with reduced critical dimensions.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. All other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the size, or scale, of the components of a typical transistor also requires being able to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, preferably in a self-aligned manner. The ability to form and pattern components such as the gate conductor and gate dielectric on such reduced scales, consistently, robustly and reproducibly, is limited by, among other things, physical limits imposed by photolithography. Diffraction effects impose limits on the critical dimensions of components such as gate conductors and gate dielectrics that correspond roughly to the wavelengths of the light used to perform the photolithography. Consequently, one conventional approach to achieving reduced critical dimensions involves retooling wafer fabs to use shorter wavelengths, as in deep ultraviolet (DUV) photolithography and/or in high-energy electron beam lithography.
However, residual nitrides at the surface of an inorganic bottom anti-reflective coating (BARC) typically used in deep ultraviolet (DUV) photolithography may cause xe2x80x9cfootingxe2x80x9d or neutralization of the Photo Acid Generator (PAG) in deep ultraviolet (DUV) photoresists at the interface between the inorganic bottom anti-reflective coating (BARC) and an overlying deep ultraviolet (DUV) photoresist layer. Footing may lead to deep ultraviolet (DUV) photolithography reworks, increasing manufacturing costs and decreasing throughput.
One conventional approach to passivating residual nitrides at the surface of inorganic bottom anti-reflective coatings (BARCs) typically used in deep ultraviolet (DUV) photolithography involves flowing oxygen (O2) during the last stages of the deposition of the inorganic bottom anti-reflective coatings (BARCs). However, this approach is often not effective at passivating the residual nitrides at the surface of the inorganic bottom anti-reflective coatings (BARCs).
Another conventional approach to passivating residual nitrides at the surface of inorganic bottom anti-reflective coatings (BARCs) typically used in deep ultraviolet (DUV) photolithography involves running the wafers through an oxygen plasma strip process after the deposition of the inorganic bottom anti-reflective coatings (BARCs). However, this approach is often not stable, and, therefore is also often not effective at passivating the residual nitrides at the surface of the inorganic bottom anti-reflective coatings (BARCs).
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided, the method including forming a gate dielectric layer above a substrate layer and forming a gate conductor layer above the gate dielectric layer. The method also includes forming an inorganic bottom anti-reflective coating layer above the gate conductor layer and treating the inorganic bottom anti-reflective coating layer with an oxidizing treatment during a rapid thermal anneal process.
In another aspect of the present invention, a semiconductor device is provided, formed by a method including forming a gate dielectric layer above a substrate layer and forming a gate conductor layer above the gate dielectric layer. The method also includes forming an inorganic bottom anti-reflective coating layer above the gate conductor layer and treating the inorganic bottom anti-reflective coating layer with an oxidizing treatment during a rapid thermal anneal process.